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21
SmartTime
21.8
SmartTime Timing Analyzer
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SmartTime
21
Introduction
21.1
Design Flows with SmartTime
21.2
Starting and Closing SmartTime
21.3
SmartTime Components
21.4
SmartTime Constraint Scenario
21.5
Setting SmartTime Options
21.6
SmartTime Tutorial
21.7
SmartTime Constraints Editor
21.8
SmartTime Timing Analyzer
21.8.1
Components of the SmartTime Timing Analyzer
21.8.2
Analyzing Your Design
21.8.3
Performing a Bottleneck Analysis
21.8.4
Managing Clock Domains
21.8.5
Managing Path Sets
21.8.6
Displaying Path List Timing Information
21.8.7
Displaying Expanded Path Timing Information
21.8.8
Using Filters
21.8.9
Cross-probing between ChipPlanner and SmartTime
21.8.10
Cross-probing Between NetlistViewer and SmartTime
21.9
Advanced Timing Analysis
21.10
Generating Timing Reports
21.11
Timing Concepts
21.12
Dialog Boxes
21.13
Menus, Tools, and Shortcut Keys
21.14
Data Change History – SmartTime
21.15
Constraints by File Format - SDC Command Reference
21.16
Design Object Access Commands
21.17
Glossary
21.18
Revision History
21
Microchip FPGA Support
21
Microchip Information
22
Timer
23
VHDL Vital Simulation
24
Verilog Simulation
25
Technical Support
26
About Microchip
21.8 SmartTime Timing Analyzer
Rev: A
