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21
SmartTime
21.6
SmartTime Tutorial
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SmartTime
21
Introduction
21.1
Design Flows with SmartTime
21.2
Starting and Closing SmartTime
21.3
SmartTime Components
21.4
SmartTime Constraint Scenario
21.5
Setting SmartTime Options
21.6
SmartTime Tutorial
21.6.1
Start the Tutorial
21.6.2
Creating a Clock Constraint
21.6.3
Adding an Input Delay Constraint
21.6.4
Adding an Output Delay Constraint
21.6.5
Analyzing the Maximum Operating Frequency
21.6.6
Viewing Register-to-Register Paths
21.6.7
Viewing External Setup Paths
21.6.8
Viewing Clock-to-Output Paths
21.7
SmartTime Constraints Editor
21.8
SmartTime Timing Analyzer
21.9
Advanced Timing Analysis
21.10
Generating Timing Reports
21.11
Timing Concepts
21.12
Dialog Boxes
21.13
Menus, Tools, and Shortcut Keys
21.14
Data Change History – SmartTime
21.15
Constraints by File Format - SDC Command Reference
21.16
Design Object Access Commands
21.17
Glossary
21.18
Revision History
21
Microchip FPGA Support
21
Microchip Information
22
Timer
23
VHDL Vital Simulation
24
Verilog Simulation
25
Technical Support
26
About Microchip
21.6 SmartTime Tutorial
Rev: A
