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Libero IDE v9.x
Libero IDE v9.x
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  2. 21 SmartTime
  3. 21.16 Design Object Access Commands
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  • 21 SmartTime
    • 21 Introduction
    • 21.1 Design Flows with SmartTime
    • 21.2 Starting and Closing SmartTime
    • 21.3 SmartTime Components
    • 21.4 SmartTime Constraint Scenario
    • 21.5 Setting SmartTime Options
    • 21.6 SmartTime Tutorial
    • 21.7 SmartTime Constraints Editor
    • 21.8 SmartTime Timing Analyzer
    • 21.9 Advanced Timing Analysis
    • 21.10 Generating Timing Reports
    • 21.11 Timing Concepts
    • 21.12 Dialog Boxes
    • 21.13 Menus, Tools, and Shortcut Keys
    • 21.14 Data Change History – SmartTime
    • 21.15 Constraints by File Format - SDC Command Reference
    • 21.16 Design Object Access Commands
      • 21.16.1 all_inputs
      • 21.16.2 all_registers
      • 21.16.3 all_registers
      • 21.16.4 get cells
      • 21.16.5 get_clocks
      • 21.16.6 get_pins
      • 21.16.7 get_nets
      • 21.16.8 get_ports
    • 21.17 Glossary
    • 21.18 Revision History
    • 21 Microchip FPGA Support
    • 21 Microchip Information
  • 22 Timer
  • 23 VHDL Vital Simulation
  • 24 Verilog Simulation
  • 25 Technical Support
  • 26 About Microchip

21.16 Design Object Access Commands

Design object access commands are SDC commands. Most SDC constraint commands require one of these commands as command arguments.

Designer software supports the following SDC access commands:

Design Object

Access Command

Cell

get_cells

Clock

get_clocks

Net

get_nets

Port

get_ports

Pin

get_pins

Input ports

all_inputs

Output ports

all_outputs

Registers

all_registers

Rev: A

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