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21
SmartTime
21.9
Advanced Timing Analysis
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SmartTime
21
Introduction
21.1
Design Flows with SmartTime
21.2
Starting and Closing SmartTime
21.3
SmartTime Components
21.4
SmartTime Constraint Scenario
21.5
Setting SmartTime Options
21.6
SmartTime Tutorial
21.7
SmartTime Constraints Editor
21.8
SmartTime Timing Analyzer
21.9
Advanced Timing Analysis
21.9.1
Understanding Inter-Clock Domain Analysis
21.9.2
Activating Inter-Clock Domain Analysis
21.9.3
Displaying Inter-Clock Domain Paths
21.9.4
Deactivating a Specific Inter-Clock Domain
21.9.5
Timing Exceptions Overview
21.9.6
Specifying a Maximum Delay Constraint
21.9.7
Specifying a Minimum Delay Constraint
21.9.8
Specifying a Multicycle Constraint
21.9.9
Specifying a False Path Constraint
21.9.10
Changing Output Port Capacitance
21.9.11
Specifying Clock Source Latency
21.9.12
Specifying Disable Timing Constraint
21.9.13
Specifying Clock-to-Clock Uncertainty Constraint
21.10
Generating Timing Reports
21.11
Timing Concepts
21.12
Dialog Boxes
21.13
Menus, Tools, and Shortcut Keys
21.14
Data Change History – SmartTime
21.15
Constraints by File Format - SDC Command Reference
21.16
Design Object Access Commands
21.17
Glossary
21.18
Revision History
21
Microchip FPGA Support
21
Microchip Information
22
Timer
23
VHDL Vital Simulation
24
Verilog Simulation
25
Technical Support
26
About Microchip
21.9 Advanced Timing Analysis
Rev: A
