15.7.12 Creating Local Clock Regions

For IGLOO, Fusion, ProASIC3, and Axcelerator families, you can use a PDC file to create local clock regions.

For ProASIC PLUS and ProASIC families, you can create local clock regions in ChipPlanner or define them in a GCF file. For more information, see the Floorplanning ProASIC/ProASIC PLUS Devices for Increased Performance application note.

For Axcelerator, you can create local clock regions in ChipPlanner or define them in a PDC file.

When you create a local clock region, the selected net and all the macros driven by that net are assigned to the local clock region.

To create a local clock region from the MVN Hierarchy window:

  1. In the Net tab of the Hierarchy window, select a clock net. Clock nets have a clock icon next to them in the Net view.
  2. From the Region menu, choose Create LocalClock.
    • ProASICPLUS or ProASIC - choose Spine
    • Axcelerator- Choose one of the following: RCLK Tile; RCLK Row; HCLK Tile; HCLK Column
  3. Drag a rectangle from the top-left corner of the new local clock region to its bottom-right corner. As you drag out the region, the rectangle snaps to the spine, tile, row or column based on the type of local clock you chose and a tooltip appears in its lower-right corner, showing how much logic, RAM blocks, and I/Os are in the region.
Note: A net that is already assigned to a local clock region cannot be assigned to another non-overlapping region.

For ProASIC and ProASIC PLUS families, the RAM blocks and I/Os are assigned to the local clock region unless the Compile option “Include RAM and I/O in Spine and Net Regions” is cleared. See "Compile Options" in the online help for more information. For Axcelerator, the RAM blocks and I/Os are always included in the local clock region.

The default name of the local clock region is LocalClock_<netname> (for example, LocalClock_exl_d_0), and its type is inclusive.

Designer does not support exclusive local clock regions. Local clock regions are inclusive by default, and you cannot change their type.

Note: ProASIC and ProASICPLUS - To assign a signal to a spine, the spine itself and the entry MUX must be free. However, this does NOT necessarily require the corresponding global network to be unused.
Note: For example, you can assign non-global signals to spines when four global networks are used by other high fan-out nets. For more information, refer to the application note Optimal Usage of Global Network Spines in ProASIC PLUS Devices, which is available from the Microchip web site.

For more information on creating and using local clock regions for Axcelerator, see the RTAX-S/SL Clocking Resource and Implementation application note, which is available from the RTAX-S Documentation web page.