15.7.14 About Quadrant Clocks

A clock conditioning circuit (CCC) can include any of the following functional block cores: CLKBUF, CLKINT, PLL, and CLKDLY. All of the CCCs include the quadrant clock feature.

You can use both CLKBUF and CLKINT as a quadrant clock driver. They can be placed in either a global or quadrant clock location.

The PLL and CLKDLY cores are options for a global or quadrant clock location.

You can instantiate as many CCC cores as you want in your design, up to the maximum allowed by the architecture (18).

Synthesis tools can only infer CLKBUF and CLKINT cores up to a total of six clocks in the design. The six clocks include any clock you instantiated using CCC cores. There is no user variable to control the maximum number of clocks available to the synthesis engines for inferring purposes.