13.23.26 Creating Your Testbench with WaveFormer Pro

WaveFormer Pro generates VHDL and Verilog testbenches from drawn waveforms. Create your testbench after you are done creating your design and wish to perform simulation. If you do not have WaveFormer Pro, create your testbench with an alternative third-party tool.

There are five basic steps for creating testbenches using WaveFormer Pro and Libero IDE. These steps are described in detail in the following sections.

To create a testbench using WaveFormer Pro:

  1. Click WaveFormer Pro in the Project Flow window. WaveFormer Pro starts and your signal information is imported automatically.
  2. Using WaveFormer Pro, draw the waveforms to describe the testbench.
  3. From the Export menu, choose Export Timing Diagram and choose the save type as *.tim or *.btim. This saves the waveforms.
  4. (Optional) Add VHDL Libraries and Use Clauses for VHDL export. These libraries or packages can be included using the VHDL Libraries and Use Clauses dialog. From the Options menu, select the VHDL Libraries and Use Clauses menu item to open this dialog.
  5. From the Export menu, choose Export Timing Diagram and choose the type of file to generate. To generate a plain testbench model (which does not instantiate your model under test), choose one of the VHDL or Verilog scripts. To simulate with the testbench model, you will need to write a top-level model that instantiates the testbench model and the model under test. Below is a list of VHDL and Verilog testbench generation scripts:
    • VHDL Wait (*.vhd)s
    • VHDL Transport (*.vhd)s
    • Verilog
  6. From the File menu, choose Exit.
Note: If you added extra signals to the testbench and do not want to export those signals, then double-click the signal’s names to open the Signals Properties dialog and clear the Export check box.

Synplify always changes the data type to std_logic or std_logic_vector in the post_synthesis netlist. If your top-level entity port is not std_logic or std_logic_vector and you need to run post-synthesis or post-layout simulation, you need to change the data type in WFL.

To create two testbenches:

  1. Open the *.tim file and select the special data type signal, right-click and choose Edit Selected Signal.
  2. Choose std_logic or std_logic_vector under VHDL and click Save.
ModelSimTM AE: ModelSim Actel Edition (AE) is a custom edition of ModelSim PE that is integrated into Libero's design environment. ModelSim for Actel is an OEM edition of Model Technology Incorporated’s (MTI) tools. ModelSim for Actel supports VHDL or Verilog. It only works with Actel libraries and is supported by Actel. Other editions of ModelSim are supported by Libero IDE. To use other editions of ModelSim with Libero IDE, simply do not install ModelSim AE from the Libero CD.
Note: ModelSim for Actel comes with its own online help and documentation. After starting ModelSim, click the Help menu.