13.23.25 WaveFormer ProTM

WaveFormer Pro can be used to generate VHDL and Verilog stimulus-based testbenches for Libero IDE. WaveFormer Pro fits into the Libero IDE, automatically extracting signal information from your HDL design files and producing HDL test bench code that can be used for VHDL or Verilog simulation.

WaveFormer Pro generates VHDL and Verilog testbenches from drawn waveforms. Use WaveFormer Pro to generate the following:

  • Reactive testbenches
  • VHDL transport testbench (*.vhd) that uses assignment statements
  • VHDL wait testbench (*.vhd) that uses wait statements
  • Verilog (*.v) file with Verilog stimulus statements
Update your project Profile to add WaveFormer Pro to your Libero IDE. See the Setting your Project Profile help topic for more information.
Note: WaveFormer Pro comes with its own online help. After starting WaveFormer Pro, click the Help menu.