5.24.17 Synplify ME and Synplify Pro ME

Libero IDEs integrated synthesis tool, Synplify Pro ME from Synopsys, takes your Verilog or VHDL Hardware Description Language source as input and outputs an optimized EDIF and HDL netlist.

Set your tool profile to the synplifypro.exe to take advantage of this tool.

See the Microchip Attribute and Directive Summary in the Synplify online help for a list of attributes related to Microchip devices.