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Libero IDE v9.x
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5
Libero IDE
5.32
Generating Programming Files
5.32.18
Specify I/O States During Programming Dialog Box
5.32.18.3
Port Name
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1
FlashROM, Analog System Builder, and Flash Memory System Builder
2
Analog System Builder, FlashROM and Flash Memory System Builder
3
ChipEditor
4
Designer Documentation Catalog
5
Libero IDE
5.1
What's New in Libero IDE v9.1
5.2
Supported Families
5.3
Project Management
5.4
Project Files
5.5
Project Options
5.6
Settings
5.7
Preferences
5.8
Project Manager Interface
5.9
Designing with Designer Block Components
5.10
Creating a Designer Block Component in Libero IDE
5.11
Creating a Designer Block Component in Designer
5.12
Instantiating a Designer Block Component in Designer
5.13
SmartDesign
5.14
Getting Started with SmartDesign
5.15
SmartDesign User Interface
5.16
Canvas View
5.17
Grid
5.18
Instance-Instance View
5.19
Schematic View
5.20
Creating a SmartDesign
5.21
Connecting Instances
5.22
Bus Interfaces
5.23
Incremental Design
5.24
Reference
5.25
Welcome to Designer
5.26
Device Selection
5.27
Design Constraints
5.28
Families Supported
5.29
Entering Constraints
5.30
Running Layout
5.31
Device Programming
5.32
Generating Programming Files
5.32.1
Generate a Programming File in FlashPoint
5.32.2
Generate a Programming File for SmartFusion
5.32.3
Generate a Programming File for CoreMP7/Cortex-M1 Device Support
5.32.4
Generate a Programming File for AFS Device Support - Designer Only
5.32.5
Generate a Programming File for Serialization Support in In House Programming (IHP)
5.32.6
Creating a Programming Database (PDB) File in Designer
5.32.7
Programming Embedded Flash Memory Block
5.32.8
Programming the FlashROM
5.32.9
Silicon Signature
5.32.10
Programming Security Settings
5.32.11
Custom Security Levels
5.32.12
Reprogramming a Secured Device
5.32.13
Custom Serialization Data for FlashROM Region
5.32.14
Custom Serialization Data File Format
5.32.15
Specifying I/O States During Programming
5.32.16
Custom I/O Settings and Boundary Scan Registers
5.32.17
Specifying I/O States During Programming - I/O States and BSR Details
5.32.18
Specify I/O States During Programming Dialog Box
5.32.18.1
Load from file
5.32.18.2
Save to file
5.32.18.3
Port Name
5.32.18.4
Macro Cell
5.32.18.5
Pin Number
5.32.18.6
I/O State (Output Only)
5.32.19
Generating Bitstream and STAPL files
5.32.20
Generating a Fuse File
5.32.21
Generating Prototype Files
5.32.22
Saving your design
5.32.23
Exiting Designer
5.33
TCL Command Reference
5.34
Project Manager Tcl Commands
5.35
Reference
5.36
Dialog Boxes
5.37
Revision History
5
Microchip FPGA Support
5
Microchip Information
6
Design Constraints for Software
7
Innoveda eProduct Designer Interface Guide - UNIX
8
Innoveda eProduct Designer Interface Guide – Windows
9
FlashPro for Software
10
SmartGen Cores Reference
11
HDL Coding Style
12
Libero IDE Documentation Catalog
13
Libero IDE
14
Antifuse Macro Library Guide for Software
15
MultiView Navigator
16
NetlistViewer (non-MVN)
17
IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
18
ProASIC and ProASIC PLUS Macro Library for Software
19
PinEditor (non-MVN)
20
SmartPower
21
SmartTime
22
Timer
23
VHDL Vital Simulation
24
Verilog Simulation
25
Technical Support
26
About Microchip
5.32.18.3 Port Name
Lists the names of all the ports in your design.
Rev: A
