1.4.7.1 HDL Source Files

<user_name>.vhd/.v – Top level design that combines all the blocks together

<user_name>_init_wrapper.vhd/.v – Initialization and configuration instantiation wrapper for this design

<common>/<Vhdl>/<Verilog>/initcfg.vhd/v - Soft IP

<common>/<Vhdl>/<Verilog>/initcfg_xa.vhd/v – Soft IP

<common>/<Vhdl>/<Verilog>/initcfg_xb.vhd/v – Soft IP

<common>/<Vhdl>/<Verilog>/initcfg_xc.vhd/v – Soft IP

<common>/<Vhdl>/<Verilog>/initcfg_xd.vhd/v -Soft IP

<common>/<Vhdl>/<Verilog>/initcfg_xe.vhd/v – Soft IP

<common>/<Vhdl>/<Verilog>/initcfg_xf.vhd/v – Soft IP

<common>/<Vhdl>/<Verilog>/numbits.vhd/v – package file