11.4.3.1 Synchronous Clear or Preset
Synchronous Clear or Preset The synchronous clear or preset register only uses part of the SMOD multiplexor, allowing for some combinability. The following example and figure below shows how to share a synchronous register with a 2:1 multiplexor.
VHDL
-- register with active low sync preset shared with a 2-to-1 mux.
library ieee;
use ieee.std_logic_1164.all;
entity dfm_sync_preset is
PORT (d0, d1: in std_logic;
clk, preset, sel: in std_logic;
q: out std_logic;
end dfm_sync_preset;
architecture behav of dfm_sync_preset is
signal tmp_sel: std_logic_vector(1 downto 0);
signal q_tmp: std_logic;
begin
process (clk) begin
tmp_sel <= preset & sel;
if (clk'event and clk ='1') then
case tmp_sel is
when "00" => q_tmp <= '1';
when "01" => q_tmp <= '1';
when "10" => q_tmp <= d0;
when "11" => q_tmp <= d1;
when others => q_tmp <= '1';
end case;
end if;
end process;
q <= q_tmp;
end behav;Verilog
/* register with active-low synchronous preset shared with
2-to-1 mux */
module dfm_sync_preset (d0, d1, clk, sync_preset, sel, q);
input d0, d1;
input sel;
input clk, sync_preset;
output q;
reg q;
always @ (posedge clk)
begin
case ({sync_preset, sel})
2'b00: q = 1'b1;
2'b01: q = 1'b1;
2'b10: q = d0;
2'b11: q = d1;
endcase
end
endmodule