11.4.3.3 Asynchronous Preset

Some synthesis tools automatically translate an asynchronous preset register into an asynchronous reset register without performance penalties. The bubbled logic can then be pushed into the surrounding logic without any delay penalty. There are various types of preset registers in the Microchip libraries. Some of the registers use two combinatorial modules (CMOD) and most use an inverter, which consumes part of the SMOD multiplexor. If your synthesis tool does not automatically translate an asynchronous preset register into a functionally equivalent asynchronous preset register using an asynchronous reset register, use the following examples to design an asynchronous reset register.

Figure 11-37. Asynchronous Reset (left) and Equivalent Asynchronous Reset (right)

Verilog Asynchronous Preset

// Active-low async preset flip-flop
module dfp (q, d, clk, preset);
input d, clk, preset;
output q;
reg q;
always @(posedge clk or negedge preset)
if (!preset)
q = 1'b1;
else
q = d;
endmodule

Verilog Equivalent Asynchronous Preset

/* Equivalent active-low async preset flip-flop, using an async reset flop with bubbled d
and q */
module dfp_r (q, d, clk, preset);
input d, clk, preset;
output q;
wire d_inv, reset;
reg q_inv;
assign d_inv = !d;
assign q = !q_inv;
assign reset = preset;
always @(posedge clk or negedge reset)
if (!reset)
q_inv = 1'b0;
else
q_inv = d_inv;
endmodule

VHDL Asynchronous Preset

-- register with active low async preset.
library ieee;
use ieee.std_logic_1164.all;
entity dfp is
port (d, clk, preset : in std_logic;
q : out std_logic;
end dfp;
architecture behav of dfp is
begin
process (clk, preset) begin
if (preset = '0') then
q <= '1';
elsif (clk'event and clk = '1') then
q <= d;
end if;
end process;
end behav;

VHDL Equivalent Asynchronous Preset

-- register with active low async preset.
library ieee;
use ieee.std_logic_1164.all;
entity dfp_r is
port (d, clk, preset : in std_logic;
q : out std_logic);
end dfp_r;
architecture behav of dfp_r is
signal reset, d_tmp, q_tmp : std_logic;
begin
reset <= preset;
d_tmp <= NOT d;
process (clk, reset) begin
if (reset = '0') then
q_tmp <= '0';
elsif (clk'event and clk ='1') then
q_tmp <= d_tmp;
end if;
end process;
q <= NOT q_tmp;
end behav;