11.2.3.4.1 8-bit Up Counter with Count Enable and Asynchronous Reset

The following examples infer an 8-bit up counter with count enable and asynchronous reset.

VHDL

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity counter8 is
port (clk, en, rst : in std_logic;
count : out std_logic_vector (7 downto 0));
end counter8;
architecture behav of counter8 is
signal cnt: std_logic_vector (7 downto 0);
begin
process (clk, en, cnt, rst)
begin
if (rst = '0') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (en = '1') then
cnt <= cnt + '1';
end if;
end process;
count <= cnt;
end behav;

Verilog

module count_en (en, clock, reset, out);
parameter Width = 8;
input clock, reset, en;
output [Width-1:0] out;
reg [Width-1:0] out;
always @(posedge clock or negedge reset)
if(!reset)
out = 8'b0;
else if(en)
out = out + 1;
endmodule