5.30.12 Running Multiple Pass Layout

Multiple Pass Layout attempts to improve layout quality by selecting from a greater number of Layout results. This is done by running individual place and route multiple times with varying placement seeds and measuring the best results with specified criteria.

Observe the following guidelines:

  • Before running Multiple Pass Layout, you need to save your design.
    • Multiple Pass Layout is supported in the following families: IGLOO, Fusion, ProASIC3, Axcelerator, ProASIC PLUS, ProASIC, SX-A, and eX.
    • Multiple Pass Layout saves your design file with the pass that has the best layout results. If you want to preserve your existing design state, you should save your design file with a different name before proceeding. To do this, from the File menu, select Save As.
    • Four types of reports (timing, maximum delay timing violations, minimum delay timing violations, and power) for each pass will be written out to the working directory to assist you in later analysis:
  • <adbFileName>_timing_r<runNum>_s<seedIndex>.rpt
  • <adbFileName>_timing_violations_r<runNum>_s<seedIndex>.rpt
  • <adbFileName>_timing_violations_min_r<runNum>_s<seedIndex>.rpt
  • <adbFileName>_power_r<runNum>_s<seedIndex>.rpt
  • <adbFileName>_iteration_summary.rpt provides additional details about the saved files

To configure your multiple pass options:

  1. When running Layout, select Use Multiple Passes in the Layout Options dialog box.
    1. Click Configure. The Multi-Pass Configuration dialog box appears.
    2. Set the options and click OK.

Number ofpasses: Set the number of passes (iterations) using the slider. 1 is the minimum and 25 is the maximum. The recommended number of passes is 5.

Start at seed index: Set the specific index into the array of random seeds which is to be the starting point for the passes.

Measurement: Select the measurement criteria you want to compare layout results against.

  • Slowest clock: Select to use the slowest clock frequency in the design in a given pass as the performance reference for the layout pass.
  • Specific clock: Select to use a specific clock frequency as the performance reference for all layout passes.
    • Timing violations: Select to use the pass that best meets the slack or timing-violations constraints. You must enter your own timing constraints through the SmartTime or SDC.
  • Maximum delay: Select to examine timing violations (slacks) obtained from maximum delay analysis.
  • Minimum delay: Select to examine timing violations (slacks) obtained from minimum delay analysis.
  • Select by: Worst Slack or Total Negative Slack to specify the slack criteria.
    • When Worst Slack is selected, the most amount of negative slack (or least amount of positive slack if all constraints are met) for each pass is identified, and then the largest value out of all passes determines the best pass.
    • When Total Negative Slack is selected, the sum of negative slacks from the first 100 paths for each pass is identified, and then the largest value out of all the passes determines the best pass. If no negative slacks exist for a pass, then the worst slack is used to evaluate that pass.
    • Stop on first path without violations: Select to stop performing remaining passes if all timing constraints have been met (when there are no negative slacks reported in the timing violations report).
    • Total power: Select to determine the best pass to be the one that has the lowest total power (static + dynamic) out of all layout passes.

Save design file for each pass: Select to save the design *.adb file for each pass. By default, only the best result is saved to your design. With this option, every pass stores its design file as <adbFileName>_r<runNum>_s<seedIndex>.adb. The "best"-pass design will also be written back to the original *.adb file. Saving all results does take more disk space, but allows you to analyze the result of each pass later in more detail. <adbFileName>_iteration_summary.rpt provides additional details about the saved files.