3.8.1 FESR – RF
Front-End Status Register
| Name: | FESR |
| Offset: | 0x100 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | ANTS | PLCK | XRDY | HBSAT | LBSAT | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
bit
This bit is reserved
and read as ‘0’.
Bit 6 – Reserved bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved bit
This bit is reserved and read
as ‘0’.
Bit 4 – ANTS Antenna Saturated
This status bit is used during
automatic antenna tuning. If the RF amplitude at the ANT_TUNE pin exceeds a value
specified by the registers FEANT.LVLC[3:0] and FEALR.RNGE[1:0], the ANTS bit is set
to ‘1’.
Bit 3 – PLCK PLL Locked
This status bit is set to
‘1’ if the PLL is locked within the time window specified by
FECR.PLCKG. It shows that a stable frequency is available from the fractional-N
PLL.
Bit 2 – XRDY XTO Ready
This status bit is set to
‘1’ if the XTO amplitude is settled and provides a reliable
clock output. If this bit is set to ‘1’, the XTO frequency is
available to the AVR and the fractional-N PLL.
Bit 1 – HBSAT LNA High-Band Saturated
This status bit is set to
‘1’ if the RF input level at RFIN_HB exceeds -39 dBm and if
FECR.HBNLB = 1.
Bit 0 – LBSAT LNA Low-Band Saturated
This status bit is set to
‘1’ if the RF input level at RFIN_LB exceeds -39 dBm and if
FECR.HBNLB = 0. Depending on FECR.HBNLB, one of the two HBSAT and
LBSAT bits is always set to ‘1’ if the RF input level exceeds -39
dBm (parameter no. 8.60 of RF Receiving Characteristics). In order to cope with higher RF levels, the FECR.ANDP register
bit can be set which attenuates the input power by 15 dB for the Low-Band or 18 dB
for the High-Band (see parameter no. 8.80 of RF Receiving Characteristics)
