3.8.6 FEPAC – RF
Front-End Power Amplifier Control Register
Name:
FEPAC
Offset:
0x105
Reset:
0x00
Bit
7
6
5
4
3
2
1
0
PACR[5:0]
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit 7 – Reserved
bit
This bit is reserved
and read as ‘0’.
Bit 6 – Reserved bit
This bit is reserved and read
as ‘0’.
Bits 5:0 – PACR[5:0] Power Amplifier Control Register
PACR[5:0] controls the current
sources in the power amplifier. With an optimized load impedance an output power
between -12 dBm and +14.5 dBm can be achieved according to the following
table.
Table 3-53. Output Power with
Optimized Load Impedance for VS_PA = 3V
FEPAC.PACR [5:0]
POUT/dBm Low-Band
POUT/dBm High-Band
FEPAC.PACR [5:0]
POUT/dBm Low-Band
POUT/dBm High-Band
0
-11.80
-12.90
32
4.72
4.08
1
-11.30
-12.33
33
5.09
4.51
2
-10.70
-11.76
34
5.57
5.01
3
-10.20
-11.10
35
6.00
5.42
4
-9.70
-10.60
36
6.41
5.79
5
-9.20
-10.00
37
6.77
6.27
6
-8.60
-9.50
38
7.19
6.70
7
-8.00
-9.00
39
7.55
7.11
8
-7.50
-8.50
40
7.98
7.47
9
-7.00
-7.90
41
8.40
7.89
10
-6.40
-7.30
42
8.79
8.25
11
-5.90
-6.80
43
9.11
8.68
12
-5.30
-6.30
44
9.46
9.10
13
-4.77
-5.70
45
9.82
9.49
14
-4.17
-5.20
46
10.18
9.81
15
-3.67
-4.60
47
10.60
10.16
16
-3.12
-4.07
48
10.89
10.52
17
-2.56
-3.47
49
11.30
10.88
18
-2.10
-2.97
50
11.62
11.30
19
-1.58
-2.42
51
12.06
11.59
20
-1.08
-1.86
52
12.39
12.00
21
-0.50
-1.40
53
12.82
12.32
22
0.00
-0.88
54
13.22
12.76
23
0.41
-0.38
55
13.58
13.09
24
1.00
0.20
56
13.95
13.52
25
1.42
0.70
57
14.22
13.92
26
1.83
1.11
58
14.41
14.28
27
2.42
1.70
59
14.49
14.65
28
2.88
2.12
60
14.60
14.65
29
3.38
2.53
61
14.60
14.65
30
3.81
3.12
62
14.60
14.65
31
4.31
3.58
63
14.60
14.65
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