3.8.3 FEEN2 – RF
Front-End Enable Register 2
| Name: | FEEN2 |
| Offset: | 0x102 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | CPBIA | XTPEN | PLPEN | TMPM | PAEN | SDTX | SDRX | |
| Access | R | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
bit
This bit is reserved
and read as ‘0’.
Bit 6 – CPBIA Cap Array
Bias
If this bit is
written to ‘1’, the DC biasing of the digital controllable
CTUNE capacitor array which is used for antenna tuning is enabled.
This has to be done in RXMode, TXMode and during the automatic antenna tuning
procedure.
Bit 5 – XTPEN XTO Voltage Pump Enable
This bit must be written to
‘1’ if the SPDT RF switch is to be used.
Bit 4 – PLPEN PLL Post Enable
This bit shall be set 10 μs
after the PLL was enabled in FEEN1.PLEN.
Bit 3 – TMPM Temperature Measurement
If this bit is written to
‘1’, the temperature measurement is activated. This bit has to
be set between FEEN1.ADEN = 1 and FEEN1.ADCLK =
1.
Bit 2 – PAEN Power Amplifier Enable
If this bit is written to
‘1’, the power amplifier biasing is enabled. It is used in
TXMode and during the automatic antenna tuning procedure. This bit enables only the
biasing, but not the current sources in the power amplifier. The current sources,
and, therefore, the RF carrier is switched on by the FSCR.PAOER register after
FEEN2.PAEN = 1 (see TX DSP). The current
sources setting for the FEPAC.PACR[7:0] power amplifier must be set before PAEN =
1.
Bit 1 – SDTX Single Pole Double Throw (SPDT) RF Switch
Tx
If this bit is written to
‘1’, the antenna port of the SPDT (pin 4/SPDT_ANT) is switched
to the power amplifier port (pin 6/SPDT_TX). The bit SDRX shall be
‘0’.
Bit 0 – SDRX Single Pole Double Throw (SPDT) RF Switch
Rx
If this bit is written to
‘1’, the antenna port of the SPDT (pin 4/SPDT_ANT) is switched
to the receive path port (pin 3/SPDT_RX). The bit SDTX is
‘0’.
