3.8.9 FEMS – RF
Front-End Main and Swallow Control Register
Name:
FEMS
Offset:
0x108
Reset:
0x00
Bit
7
6
5
4
3
2
1
0
PLLM[3:0]
PLLS[3:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 7:4 – PLLM[3:0] Fractional-N PLL M
Value
PLLM[3:0] sets the M
counter divider ratio used for the fractional-N PLL.
Bits 3:0 – PLLS[3:0] Fractional-N PLL S Value
PLLS[3:0] sets the S counter
divider ratio used for the fractional-N PLL. The values must be copied to the PLL
register before using the RF front end. Firmware does this by
default.
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