3.8.14 FEANT – RF Front-End Antenna

Name: FEANT
Offset: 0x10D
Reset: 0x00

Bit 76543210 
 LVLC[3:0] 
Access RRRRR/WR/WR/WR/W 
Reset 00000000 

Bit 7 –  Reserved bit

This bit is reserved and read as ‘0’.

Bit 6 –  Reserved bit

This bit is reserved and read as ‘0’.

Bit 5 –  Reserved bit

This bit is reserved and read as ‘0’.

Bit 4 –  Reserved bit

This bit is reserved and read as ‘0’.

Bits 3:0 – LVLC[3:0] Level Control

LVLC[3:0] determines the output voltage of the integrated DAC used for RF amplitude measurement during the automatic antenna tuning procedure. The output of the DAC is compared with the output voltage of the amplitude detector and the result of this comparison can be read from FESR.ANTS.