3.10.8.3.2 SPSR – SPI
Status Register
| Name: | SPSR |
| Offset: | 0x02D |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | SPIF | | TXIF | | RXIF | | | SPI2X | |
| Access | R | R | R | | R | R | R | R/W | |
| Reset | 0 | 0 | 0 | | 0 | 0 | 0 | 0 | |
Bit 7 – SPIF SPI Interrupt
Flag
When a serial transfer is
complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and
global interrupts are enabled. If NSS is an input and is driven low when the SPI is
in host mode, this also sets the SPIF flag. SPIF is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, the SPIF bit
can be cleared by first reading the SPI status register with SPIF set, then
accessing the SPI data register (SPDR).
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – TXIF Transmit Buffer
Interrupt Flag
The TXIF bit is set if the SPI
transmit buffer has reached the defined fill level as in TIL[2:0] of SFIR. An
interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. The
TXIF bit is cleared if new data is written to the SPDR and the fill level of the
buffer has exceeded the defined interrupt level.
Bit 3 – RXIF Receive Buffer
Interrupt Flag
The RXIF bit is set if the SPI
receive buffer has reached the defined fill level as in RIL[2:0] of SFIR. An
interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. The
RXIF bit is cleared if data were read from SPDR and the fill level of the buffer has
fallen below the defined interrupt level.
Bit 3 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 2 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 1 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 0 – SPI2X Double SPI
Speed
If this bit is written to
logic ‘1’, the SPI speed (SCK frequency) will be doubled when the
SPI is in host mode. This means that the minimum SCK period will be two CPU clock
periods. When the SPI is configured as a client, the SPI is only ensured to work at
CLKI/O/4 or lower.
