This bit causes the SPI
interrupt to be executed if the SPIF bit in the SPSR register is set and if the
global interrupt enable bit in SREG is set.
Bit 6 – SPE SPI
Enable
When the SPE bit is written to
‘1’, the SPI is enabled. This bit must be set to enable any SPI
operations.
Bit 5 – DORD Data
Order
If the DORD bit is written to
‘1’, the LSB of the data word is transmitted first. If the DORD
bit is written to ‘0’, the MSB of the data word is transmitted
first.
Bit 3 – MSTR Host/Client
Select
This bit selects SPI Host mode
when written to ‘1’ and client SPI mode when written to logic
‘0’. If NSS is configured as an input and is driven low while
MSTR is set, MSTR is cleared and SPIF in SPSR is set. The user then has to set MSTR
to re-enable SPI Host mode.
Bit 3 – CPOL Clock
Polarity
If this bit is written to
‘1’, SCK is high when idle. If CPOL is written to
‘0’, SCK is low when idle. Refer to Figure 3-90 and Figure 3-91 for an example. The CPOL functionality is summarized in the
following table.
Table 3-105. CPOL
Functionality
CPOL
Leading Edge
Trailing Edge
0
Rising
Falling
1
Falling
Rising
Bit 2 – CPHA Clock
Phase
The setting of the clock phase
(CPHA) determines if data is sampled on the leading (first) or trailing (last) edge
of SCK. Refer to Figure 3-90 and Figure 3-91 for an example. The CPHA functionality is summarized in the
following table.
Table 3-106. CPHA
Functionality
CPHA
Leading Edge
Trailing Edge
0
Sample
Setup
1
Setup
Sample
Bits 1:0 – SPR[1:0] SPI Clock Rate
Select
These two bits control the SCK
rate of the device configured as a host. SPR[1:0] has no effect on the client. The
relationship between SCK and the CLKI/O is shown in the following table.
Table 3-107. Relationship Between
SCK and Oscillator Frequency
SPSR.SPI2X
SPR1
SPR0
SCK Frequency
0
0
0
CLKI/O/4
0
0
1
CLKI/O/16
0
1
0
CLKI/O/64
0
1
1
CLKI/O/128
1
0
0
CLKI/O/2
1
0
1
CLKI/O/8
1
1
0
CLKI/O/32
1
1
1
CLKI/O/64
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