3.10.8.3.3 SFFR – SPI FIFO
Fill Status Register
| Name: | SFFR |
| Offset: | 0x157 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | TFC | TFL[2:0] | RFC | RFL[2:0] | |
| Access | W | R | R | R | W | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – TFC Transmit Buffer Clear
Writing a ‘1’
to this bit clears the transmit buffer and resets the fill level counter to
‘0’.
Bits 6:4 – TFL[2:0] Transmit Buffer Fill Level
The SPI transmit buffer fill
level is a read-only register, which holds the current fill level of the SPI
transmit buffer.
Bit 3 – RFC Receive Buffer Clear
Writing a ‘1’
to this bit clears the receive buffer and resets the fill level counter to
‘0’.
Bits 2:0 – RFL[2:0] Receive Buffer Fill
Level
The SPI receive
buffer fill level is a read-only register, which holds the current fill level of the
SPI receive buffer.
