3.10.8.3.4 SFIR – SPI FIFO Interrupt Register
| Name: | SFIR |
| Offset: | 0x158 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| STIE | TIL[2:0] | SRIE | RIL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – STIE SPI Transmit Buffer Interrupt Enable
This bit causes the SPI transmit buffer interrupt to be executed if the TXIF bit in the SPSR register is set and if the global interrupt enable bit in SREG is set.
Bits 6:4 – TIL[2:0] Transmit Buffer Interrupt Level
The SPI transmit buffer interrupt level is a read/write register,
which holds the fill level that triggers an SPI interrupt. If it is set to
‘0’, an interrupt is triggered from the transmit FIFO when
the last byte was transferred from the transmit buffer to the serial shift
register. If it is set to ‘1’, it issues an interrupt when only
one byte is left in the buffer.
Bit 3 – SRIE SPI Receive Buffer Interrupt Enable
This bit causes the SPI receive buffer interrupt to be executed if the RXIF bit in the SPSR register is set and if the global interrupt enable bit in SREG is set.
Bits 2:0 – RIL[2:0] Receive Buffer Interrupt Level
The SPI receive buffer interrupt level is a read/write register,
which holds the fill level that triggers an SPI interrupt. If it is set to
‘0’, no interrupt is triggered from the receive FIFO. Set
to ‘1’, it issues an interrupt when 1 byte is captured and
written to the buffer.