3.10.7.4 Timer3

The 16-bit timer/counter unit allows accurate program execution timing (event management), wave generation and signal timing measurement. The main features are:

  • Four different selectable input clocks
  • One output compare unit
  • One input capture unit
  • Input capture noise canceller
  • Clear timer on compare match or capture event
  • Variable PWM period
  • Frequency generator
  • External event counter
  • Three independent interrupt sources (T3CAP, T3COM, T3OVF)
Figure 3-78. Timer3 Block Diagram

Timer 3 consists of a 6-bit prescaler and a 16-bit up counter with two compare registers (T3CORH, T3CORL) and two capture registers (T3ICRH, T3ICRL). The timer can be used as an event counter, timer or signal generator. Its output can be programmed as modulator. The compare registers enable it for various modes of signal generation and modulation. The counter can be driven by several clock sources. For an external capture input signal (TICP), it has a programmable edge sensitive input that can be used as capture signal input. The current counter value is readable via its capture register after a software capture event. In the capture mode, the counter value can be also captured by a programmable capture event from the Timer2 clock output (CLKT2), transparent RX path A (TRPA), transparent RX path B (TRPB) from the UHF receiver or the slow RC oscillator clock (CLKSRC).

The comparator output is controlled by a control register (T3CR) that contains mask bits for actions (counter reset, output toggle, timer interrupt) that can be triggered by a compare match event, capture event or the counter overflow. The output compare registers (T3CORH, T3CORL) are compared with the counter value at all times. The result of the compare can be routed to the PC3 output pin by the TX modulator.

Interrupt request signals are all visible in the timer interrupt flag register (T3IFR). All interrupts are individually maskable with the timer interrupt mask register (T3IMR).

The counter input clock (CL3) can be supplied via the T clock of the system clock prescaler (CLKT), the XTO based clock (CLKXTO2, CLKXTO4) or the internal fast oscillator clock (CLKFRC).

The 6-bit prescaler works together with the counter stage (T3CNT). The counter stage has six input signals (CL3, CLKT2, TRPA, TRPB, TICP, CLKSRC) and four output signals (T3CAP, T3OVF, T3COM and CLKT3). The CL3 supplies the 6-bit prescaler with a clock. The CLKT2, the UHF-receiver-transparent RX path A, B outputs (TRPA, TRPB), the external input capture signal (TICP), or CLKSRC can capture the counter value in the capture register. The CLKT3 is the output clock and T3CAP, T3OVF and T3COM are the interrupt request signals of the counter stage.

Figure 3-79. Timer3 Counter Stage

Signal description of Timer3 (internal signals):

CLKT2 – Timer2 counter stage clock input

TRPA – Transparent UHF receiver data path A input signal TRPB Transparent UHF receiver data path B input signal

TICP – Timer3 external input capture

CLKSRC – Slow RC oscillator clock input

CL3 – Selected prescaler input clock

CL3P – Counter input clock

CMR – Counter compare register match

RES – Counter reset (clear all bits)

OVF – Counter overflow

CP – Capture event signal

CPR – Capture event reset signal

CLKT3 – Counter stage clock output

T3CAP – Timer3 capture event interrupt

T3OVF – Timer3 counter overflow interrupt

T3COM – Timer3 compare match interrupt

M3 – Modulator output toggle flip-flop

Modulator Toggle Flip-Flop (T3)

The toggle flip-flop (T3) consists of a flip-flop with a preset input signal (T3TOP), an input clock (CLKT3) and an output signal (M3). The T3TOP bit in the T3CR register allows the programmer to initialize the toggle flip-flop output (M3) only if Timer3 is not running (T3ENA = 0). The output signal (M3) is inverted with every rising edge of the input clock (CLKT3).Figure 3-80 shows the toggle flip-flop (T3).

Figure 3-80. Toggle Flip-Flop T3