3.10.7.6 Timer5

The 16-bit Timer5 unit allows accurate program execution timing (event management). The main features are:

• Synchronous operation
• One output compare unit
• Clear timer on compare match (Auto Reload)
• Two independent interrupt sources (T5OFF and T5COF)

A simplified block diagram of the synchronous 16-bit Timer5 is shown in the following figure. The CPU-accessible I/O registers, including I/O bits and I/O pins, are shown in bold.

The PRT5 bit in “PRR1 – Power reduction register 1” must be written to ‘0’ to enable the Timer5 module.

The counter register (T5CNT) and the output compare register (T5OCR) are both 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the Accessing 16-bit Registers. The Timer5 control register (T5CCR) is an 8-bit register and has no CPU access restrictions.

Interrupt requests (abbreviated to Int.Req. in the figure) signals are visible in the Timer5 interrupt flag register (T5IFR). Both interrupts are individually masked with the timer interrupt mask register (T5IMR). T5IFR and T5IMR are not shown in the figure.

Timer5 is clocked internally via the prescaler. The clock select logic block controls which clock source the counter uses to increment its value. The counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (CLK_T5).

The output compare register (T5OCR) is compared with the counter value at all time. The compare match event sets the compare match flag (T5COF), which can be used to generate an output compare interrupt request.

The T5CNT and T5OCR are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte-accessed using two read or write operations. The 16-bit timer has a single 8-bit register for temporarily storing the high byte of the 16-bit access. The same temporary register is shared among all 16-bit registers within Timer5. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register and the low byte are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle.

Not all 16-bit accesses use the temporary register for the high byte. Reading the T5OCR 16-bit register does not involve using the temporary register.

To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte.

The following code examples show how to access the 16-bit timer registers, assuming that no interrupts update the temporary register. The same principle can be used for accessing the T5OCR register directly. Note that when using “C” the compiler handles the 16-bit access.

The assembly code example returns the T5CNT value in the r17:r16 register pair.

It is important to note that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer registers, the result of the access outside the interrupt is corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable interrupts during 16-bit access.

The following code examples show how to perform an atomic read of the T5CNT register contents. Reading the T5OCR register can be done using the same principle.

The assembly code example returns the T5CNT value in the r17:r16 register pair.

The following code examples show how to do an atomic write of the T5CNT Register contents. Writing to the T5OCR register can be done using the same principle.

The assembly code example requires the r17:r16 register pair to contain the value to be written to T5CNT.

If writing to more than one 16-bit register where the high byte is the same for all registers written, the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case.

Timer5 is clocked by an internal clock source. The clock source is selected by the clock select logic which is controlled by the clock select (T5CS[2:0]) bits located in the Timer5 control register (T5CCR). For details on clock sources and the prescaler, see Timer5 Prescaler.

The main part of the 16-bit timer is the programmable 16-bit counter unit. The following figure shows a block diagram of the counter and its surroundings.

Signal description (internal signals):

Count – Increment T5CNT by 1.

Clear – Clear T5CNT (set all bits to ‘0’).

CLK_T5 – Timer5 clock.

The 16-bit counter is mapped into two 8-bit I/O memory locations: counter high (T5CNTH) containing the upper eight bits of the counter, and counter low (T5CNTL) containing the lower eight bits. The T5CNTH register can only be indirectly accessed by the CPU. When the CPU does an access to the T5CNTH I/O location, the CPU accesses the high byte temporary register (TEMP). The temporary register is updated with the T5CNTH value when the T5CNTL is read, and T5CNTH is updated with the temporary register value when T5CNTL is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to note that in some circumstances writing to the T5CNT register while the counter is counting produces unpredictable results. The special cases are described in the sections where they are of importance.

Depending on the operating modes used, the counter is cleared or incremented at each timer clock (CLK_T5). The CLK_T5 is generated from an internal clock source, selected by the clock select bits (T5CS[2:0]). When no clock source is selected (T5CS[2:0] = 0b000), the timer is stopped. However, the T5CNT value can be accessed by the CPU, independent of whether CLK_T5 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.

The 16-bit comparator continuously compares T5CNT with the output compare register (T5OCR). If T5CNT equals T5OCR, the comparator signals a match. A match sets the output compare flag (T5COF) at the next timer clock cycle. If enabled (T5CIM = 1), the output compare flag generates an output compare interrupt. The T5COF flag is automatically cleared when the interrupt is executed. Alternatively, the T5COF flag can be cleared by software by writing a logical ‘1’ to its I/O bit location. The following figure shows a block diagram of the output compare unit. The elements of the block diagram that are not directly a part of the output compare unit are shaded in gray.

Compare Match Blocking by T5CNT Write

All CPU writes to the T5CNT register blocks any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows T5OCR to be initialized to the same value as T5CNT without triggering an interrupt when the Timer5 clock is enabled.

Using the Output Compare Unit

Because writing T5CNT in any operating mode blocks all compare matches for one timer clock cycle, changing T5CNT poses risks when using any of the output compare channels, regardless of whether the timer is running or not. If the value written to T5CNT equals the T5OCR value, the compare match is missed.

Internal Clock Source

Timer5 can be clocked directly by the system clock (by setting the T5CS[2:0] = 0b001). This provides the fastest operation, with a maximum clock frequency equal to system clock frequency (f_{CLK_I/O}). Alternatively, one of the taps from the prescaler can be used as a clock source by setting the T5CS[2:0]. See Table 3-102 for Timer5 settings. The prescaled clock has a frequency of either f_{CLK_I/O}/8, f_{CLK_I/O}/32, f_{CLK_I/O}/64, f_{CLK_I/O}/128, f_{CLK_I/O}/256 or f_{CLK_I/O}/1024.

Prescaler Reset

The prescaler is free-running, meaning it operates independently of the clock select logic of Timer5. The prescaler is not affected by the clock select of the timer; therefore, the state of the prescaler has implications for situations where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > T5CS[2:0] > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor.

It is possible to use the prescaler reset for synchronizing Timer5 to program execution.