3.10.7.3 Timer2

Timer2 is designed to be used mainly to generate periodical interrupts with high accuracy over a wide timing range; for example, sleep and polling times can be realized in 1% steps for periods from 50 ms to 1000 ms with the SRC (125 kHz) and the divided XTO clock. Divider inaccuracy due to the prescaler can be compensated by firmware. This is done by either modifying the compare register value on every nth cycle or by omitting a complete compare match at periodic intervals.

  • 8-bit timer/counter with 17-bit prescaler and compare modes
  • True 8-bit design (i.e., allows 8-bit PWM)
  • Four different selectable input clocks
  • One output compare unit
  • Clear timer on compare match
  • Different programmable PWM period
  • Frequency generator
  • External event counter
  • Two independent interrupt sources (T2COM, T2OVF)
Figure 3-73. Timer2 Block Diagram

Timer2 consists of a 17-bit prescaler and an 8-bit up counter stage with compare register (T2COR). The timer can be used as an event counter, timer and signal generator. The counter can be driven by internal and external clock sources. The 8-bit counter must be read via AVR only when the timer is stopped. Otherwise unpredictable values can be read from the asynchronous counter register. Its output clock (CLKT2) can be used to supply the TX modulator with a clock.

The Timer2 control and mode registers (T2CR, T2MR) are 8-bit registers. The comparator output is controlled by a control register (T2CR) and contains mask bits for the actions (counter reset, output toggle, timer interrupt), which can be triggered by a compare match event or by counter overflow. This architecture enables the timer for various modes.

Interrupt request signals are all visible in the timer interrupt flag register (T2IFR). All interrupts are individually maskable with the timer interrupt mask register (T2IMR).

The counter input clock (CL2) can be supplied via the T clock of the system clock prescaler (CLKT), the crystal-oscillator- based clock (CLKXTO4), the internal SRC clock (CLKSRC) or the internal FRC clock (CLKFRC).

The output compare register (T2COR) is compared with the counter value at all times. The result of the compare can be routed to the PC3 output pin by the TX modulator. T2COR can be modified while the timer is running.

The 15-bit prescaler works together with an additional 2-bit duty cycle generator as a 16-bit prescaler for 50% duty cycle output and it can be used as a 17-bit prescaler with odd duty cycles. The counter stage has one input signal (CL2) and five output signals (T2OVF, T2COMP, CLKDCG2, M2 and CLKT2). The M2, CLKT2 and CLKDCG2 are the output clocks. T2OVF and T2COMP are the interrupt request signals of the counter stage.

Figure 3-74. Timer2 8-Bit Counter Stage

Signal description of the Timer2 (internal signals):

CL2 – Prescaler input clock

CLKDCG2 – Timer2 input clock and duty cycle generator output clock

CL2P – Prescaler output clock and duty cycle generator (DCG) input clock T2OVF Timer2 counter overflow interrupt

T2COMP – Timer2 compare match interrupt

CLKT2 – Timer2 stage output clock

M2 – Modulator output toggle flip-flop

CMR – Counter compare register match

RES – Counter reset (clear all bits)

OVF – Counter overflow

Modulator Toggle Flip-Flop (T2)

The toggle flip-flop (T2) consists of a flip-flop with a preset input signal (T2TOP), an input clock (CLKT2) and an output signal (M2). The T2TOP bit at the T2CR register allows the programmer to initialize the toggle flip-flop output signal (M2) only if Timer2 is not running (T2ENA = 0). The output signal (M2) is inverted with every rising edge of the input clock (CLKT2). The following figure shows the toggle flip-flop (T2).

Figure 3-75. Toggle Flip-Flop (T2)
Figure 3-76. Example of Toggle Flip-Flop T2 Operation