3.10.7.2 Timer1

This timer can be used to generate real time clock (RTC) interrupts and clock output. Main features:

  • 8-bit timer/counter with 17-bit prescaler and compare modes
  • True 8-bit design (i.e., allows 8-bit PWM)
  • Four different selectable input clocks
  • One output compare unit
  • Clear timer on compare match
  • Programmable PWM period
  • Frequency generator
  • External event counter
  • Two independent interrupt sources (T1COM, T1OVF)
Figure 3-70. Timer1 Block Diagram

Timer1 consists of a 17-bit prescaler and an 8-bit up counter stage with compare register (T1COR). The timer can be used as an event counter, timer and signal generator. The counter can be driven by internal and external clock sources. The 8-bit counter is readable via AVR only when the timer is stopped.

The Timer1 control and mode registers (T1CR, T1MR) are 8-bit registers. The comparator output is controlled by a control register (T1CR) and contains the mask bits for the actions (counter reset, output toggle, timer interrupt), which can be triggered by a compare match event or by counter overflow. This architecture enables the timer for various modes.

Interrupt request signals are all visible in the Timer1 interrupt flag register (T1IFR). All interrupts are individually maskable with the Timer1 interrupt mask register (T1IMR).

The counter input clock (CL1) can be supplied via the T clock of the system clock prescaler (CLKT), the crystal-oscillator-based clock (CLKXTO4), the internal SRC clock (CLKSRC) or the internal fast RC clock (CLKFRC).

The output compare register (T1COR) is compared with the counter value at all times. T1COR can be modified while the timer is running.

The 15-bit prescaler works together with an additional 2-bit duty cycle generator as a 16-bit prescaler for 50% duty cycle output or 17-bit prescaler with odd duty cycles. The counter stage has one input signal (CL1) and five output signals (T1OVF, T1COMP, CLKDCG1, M1 and CLKT1). The M1, CLKT1 and CLKDCG1 are the output clocks; T1OVF and T1COMP are the interrupt request signals of the counter stage.

Figure 3-71. Timer1 8-Bit Counter Stage

Signal description of the Timer1 (internal signals):

CL1 – Prescaler input clock

CLKDCG1 – Timer1 input clock and duty cycle generator output clock

CL1P – Prescaler output clock and duty cycle generator (DCG) input clock T1OVF Timer1 counter overflow interrupt

T1COMP – Timer1 compare match interrupt

CLKT1 – Timer1 counter stage output clock

M1 – Modulator output toggle flip-flop

CMR – Counter compare register match

RES – Counter reset (clear all bits)

OVF – Counter overflow