30.6.8 Peripheral Module Disable 8 Control Register
Note:
- When a peripheral is disabled (PMD
=
1), its clocks are gated off and its Reset is asserted, providing a reduced power consumption. - Since the Reset to the peripheral
is asserted when PMD =
1, the module’s registers must be reinitialized to their desired values whenever the corresponding PMD bit is cleared.
| Name: | PMD8(1,2) |
| Offset: | 0xFB2 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| OPAMPMD | SENT1MD | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLC4MD | CLC3MD | CLC2MD | CLC1MD | BIASMD | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 13 – OPAMPMD Op Amp Module Disable bit
| Value | Description |
|---|---|
| 1 |
Op Amp module is disabled |
| 0 |
Op Amp module is enabled |
Bit 11 – SENT1MD SENT1 Module Disable bit
| Value | Description |
|---|---|
| 1 | SENT1 module is disabled |
| 0 | SENT1 module is enabled |
Bit 5 – CLC4MD CLC4 Module Disable bit
| Value | Description |
|---|---|
| 1 | CLC4 module is disabled |
| 0 | CLC4 module is enabled |
Bit 4 – CLC3MD CLC3 Module Disable bit
| Value | Description |
|---|---|
| 1 | CLC3 module is disabled |
| 0 | CLC3 module is enabled |
Bit 3 – CLC2MD CLC2 Module Disable bit
| Value | Description |
|---|---|
| 1 | CLC2 module is disabled |
| 0 | CLC2 module is enabled |
Bit 2 – CLC1MD CLC1 Module Disable bit
| Value | Description |
|---|---|
| 1 | CLC1 module is disabled |
| 0 | CLC1 module is enabled |
Bit 1 – BIASMD Current Bias Module Disable bit
| Value | Description |
|---|---|
| 1 | Current bias module is disabled |
| 0 | Current bias module is enabled |