30.6.7 Peripheral Module Disable 7 Control Register

Note:
  1. When a peripheral is disabled (PMD = 1), its clocks are gated off and its Reset is asserted, providing a reduced power consumption.
  2. Since the Reset to the peripheral is asserted when PMD = 1, the module’s registers must be reinitialized to their desired values whenever the corresponding PMD bit is cleared.
Name: PMD7(1,2)
Offset: 0xFB0

Bit 15141312111098 
       CMP2MDCMP1MD 
Access R/WR/W 
Reset 00 
Bit 76543210 
     PTGMD    
Access R/W 
Reset 0 

Bit 9 – CMP2MD Comparator 2 Disable bit

ValueDescription
1

Comparator 2 module is disabled
0

Comparator 2 module is enabled

Bit 8 – CMP1MD Comparator 1 Disable bit

ValueDescription
1

Comparator 1 module is disabled
0

Comparator 1 module is enabled

Bit 3 – PTGMD PTG Module Disable bit

ValueDescription
1

PTG module is disabled
0

PTG module is enabled