5.15.9 INTERRUPT/WAKE-UP EVENT DELAY (NIRQ)

Frequent interrupt or wake-up events can require significant microcontroller processing time because the NIRQ pin is asserted each time an interrupt/wake-up event is generated. Therefore, the device incorporates an interrupt/wake-up delay timer (t_{d_evt_cap}) to limit the frequency of interrupt events.

When one of the event capture status bits is cleared, the NIRQ pin is deasserted, and the event delay timer starts. If further events occur while the event delay timer is running, the relevant status bits are set and NIRQ stays deasserted. As soon as the event timer expires, and one or more events are pending, the NIRQ pin is asserted again to alert the microcontroller.

We use the term microcontroller often in this data sheet without referring to a host. Mentioning a host is only necessary when discussing the SPI host.

This way, the microcontroller is interrupted only once to process several events, rather than several times to process each individual event. If the microcontroller has cleared all active event capture bits before the event delay timer expires, the NIRQ pin remains deasserted, presuming no new or pending events occurred.

The event capture registers can be read at any time.