5.15.5 VGS MONITORING AND EXTERNAL MOSFET PROTECTION

The ATA6847 monitors the gate supply voltage for each of the low and high-side external MOSFETs. The VG pin buffers the low-side gate supply voltage, whereas the VCP pin buffers the high-side gate supply voltage. The device provides two undervoltage detection thresholds, valid for both low and high-side gate supply voltages. The used threshold can be selected via the UVVGSLVL bit (see GDUCR4 Register).

A gate supply undervoltage condition for the low-side gate drivers occurs if V_VG – V_GND < V_{VGS_UV_Set_x}.

A gate supply undervoltage condition for the high-side gate drivers occurs if V_VCP – V_VDH < V_{VGS_UV_Set_x}.

The external MOSFET gate source (VGS) undervoltage monitoring is active as soon as the VG and VCP regulators are enabled, and the UVVGSEN bit is set (see GDUCR4 Register). Both the VG and VCP regulators start operating when the transition to GDU Normal mode occurs. Transitioning to GDU Standby mode is not possible unless VG and VCP are within the valid range. The status of both VG and VCP output regulators can be seen in the DSR2 register (see DSR2 Register).

The VGS undervoltage event capturing is active in GDU Standby mode and GDU Normal mode. In GDU Standby mode, the VGS undervoltage event is filtered with t_{VGS_U_V_Blank_ADOO}, ensuring the VG and VCP regulators ramp up properly. The delay filter is activated only once, when both VG and VCP regulators are activated. In case the VG and/or VCP regulator/s are not able to reach the requested voltage level (undervoltage level) within the filter time, NIRQ will be asserted.