5.15.7 VDS DRAIN-SOURCE VOLTAGE MONITORING AND POWER STAGE SHORT CIRCUIT PROTECTION

(Submit Feedback)

Short circuits in the half-bridge circuitry are monitored by sensing the voltage drop across the drain source of the external high-side and low-side MOSFETs. Comparators monitor the voltage drop between the drain (VDH) and the source terminals (SHx) of the external high-side MOSFET transistors, as well as between the external low-side MOSFET transistors drain (SHx) and source (GND in ATA6847 or SL in ATA6847L). The voltage drop is monitored during the ON phase of the MOSFET, according to the ILx and NIHx pins.

The voltage drop is compared with the reference voltage. As soon as one of the drain-source voltage drops exceed the V_SCREF threshold, a short circuit in this branch is detected.

The Short Circuit Reference Threshold (V_SCREF) can be configured via SPI, using the SCTHSEL [2:0] bits (see table Short Circuit Detection Threshold).

The following actions occur in case of a short circuit event. The corresponding interrupt register will be set according to the SIR3 Register. The short circuit event will be signaled at the interrupt output pin (NIRQ). The GDU will be switched to GDU Standby mode, and all gate driver outputs will be disabled if SCSDEN bit is set to ‘1’. If the SCSDEN bit is set to ‘0’, the device will only indicate the event at the NIRQ pin, and the gate control will not be disabled.

To prevent false short circuit triggering, a VDS Drain-Source Short Circuit event is blanked out with the edge blanking time using the EGBLT bits (GDUCR2 Register). Furthermore, the VDS short circuit event is filtered, and the filter time can be configured using the SCFLT[3:0] bits (see the SCPCR Register).