19.11.18 CoreSight ROM Table Memory Type Register

Table 19-23. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	MEMTYPE
Offset:	0x1fcc
Reset:	0x00000000
Property:	R


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
								SYSMEM
Access								HS/HC/R
Reset								0

Bit 0 – SYSMEM System Memory

Value of this register field is set to 1 when CPU0 effective DAL is DAL1 or DAL2 otherwise set to 0.

This bit indicates whether system memory is present on the bus that connects to the ROM table. This bit is set at power-up when DAL.CPU0 is greater than 0 indicating that the system memory is accessible from a debug adapter.

This bit is cleared at power-up when DAL.CPU0 is equal to 0 indicating that the system memory is not accessible from a debug adapter.

Value	Description
1	System memory is also present on this bus
0	System memory not present on bus. This is a dedicated debug bus.