19.11.12 CoreSight ROM Table Entry N Register

Table 19-17. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	ENTRY2
Offset:	0x1008
Reset:	0x00000002
Property:	R


Bit	31	30	29	28	27	26	25	24
	ADDOFF[19:12]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	ADDOFF[11:4]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ADDOFF[3:0]
Access	R	R	R	R
Reset	0	0	0	0


Bit	7	6	5	4	3	2	1	0
							FMT	EPRES
Access							R	R/HS/HC
Reset							1	0

Bits 31:12 – ADDOFF[19:0] Base Address

Base address of the component, relative to the base address of this ROM Table.

Bit 1 – FMT CoreSight Rom Table Format

Value	Description
1	32-bit format
0	8-bit format

Bit 0 – EPRES Entry Present

This bit is set to 0 by hardware under the following conditions DAL.CPU0 == DAL0 or n > DSU_CPU_NUM, meaning the CPU interface does not exist, or ext_cpu_me[n] == 0 when n <= DSU_CPU_NUM, meaning the CPU exists but is disabled otherwise this bit is set to DSU_CORESIGHT_ENTRY[n][0].

Value	Description
1	Entry present
0	Entry not present