19.11.1 Control A REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLA |
| Offset: | 0x0 |
| Reset: | 0x00000000 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PRIV | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 2 – PRIV
DAPAHB access to DSU Internal Address Space registers are also affected by PRIV setting. If PRIV=1, non-privileged DAP AHB accesses to DSU Internal Address Space registers return an AHB Client bus error. DSU External address space and DSU CoreSight ROM Address Space are not affected by the PRIV bit.
| Value | Description |
|---|---|
| 1 | Internal Address Space registers only accessible in privileged mode. |
| 0 | Internal Address Space registers accessible in privileged and unprivileged modes. |