19.11.24 CoreSight Peripheral Identification 1 Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | PID1 |
| Offset: | 0x1fe4 |
| Reset: | 0x0000009C |
| Property: | R |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DES0[3:0] | PART1[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | |
Bits 7:4 – DES0[3:0]
Bits 3:0 – PART1[3:0]
These bits will always return 0xC when read, indicating that this device implements a DSU module instance.