4.3.2.3 External Feedback Mode

In this mode, the feedback clock port (FB_CLK) is exposed to the user. The PLL clock output 0 must be connected to FB_CLK either through a global clock network or PCB routing. The following figure highlights the external feedback path routed through a global clock network. The external feedback mode allows users to adjust the clock automatically to compensate for clock network skew and/or PCB routing skew. This mode exhibits more jitter on the PLL outputs compared to the other modes.

In this mode, the VCO operates at (REF_CLK × 4 × OUTDIVx × FBDIV)/RFDIV. Any FBDIV value from 1 to 1250 is valid. In this mode, the PLL output, which is fed back as feedback clock (FB_CLK) is phase aligned with the PLL reference clock. The CCC configurator adds soft-logic around the PLL to ensure proper alignment of the PLL outputs. For information about required PLL_POWERDOWN_N input control when configured in this mode, see Power-Down Input.