4.3.1.5 Power-Down Input

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The active-low power-down input (PLL_POWERDOWN_N) from the FPGA fabric forces the PLL to its lowest power state, and the clock outputs are driven low. The PLL_POWERDOWN_N is an asynchronous signal, which can be used to reset the PLL.

Important: When the PLL is configured in internal post-divider or the external feedback mode, the PLL_POWERDOWN_N input must be controlled and de-asserted synchronously. For an example circuit, see PolarFire Family FPGA Power-Up and Resets User Guide.

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