4.3.2.2 Internal Post-Divider Feedback Mode

In this mode, one of the output dividers is placed into the feedback loop, as highlighted in the following figure. The VCO operates at (REF_CLK × 4 × OUTDIVx × FBDIV)/RFDIV. This mode supports a greater range of output frequencies than the range possible with internal Post-VCO feedback mode. The OUTDIV2 and OUTDIV3 can be cascaded to generate a clock up to 127 × 127 slower than the VCO clock. The CCC configurator adds soft-logic around the PLL to ensure proper alignment of the PLL outputs. In this mode, the PLL does not compensate for global clock network delay. For information about required PLL_POWERDOWN_N input control when configured in this mode, see Power-Down Input.