4.16.17.18 PMC Status Register

Name: PMC_SR
Offset: 0x0068
Reset: 0x00030008
Property: Read-only

Bit 3130292827262524 
      MCKXRDYPLL_INTGCLKRDY 
Access RRR 
Reset 000 
Bit 2322212019181716 
 MCKMON XT32KERRFOSCFDSCFDEVMOSCRCSMOSCSELS 
Access RRRRRRR 
Reset 0000011 
Bit 15141312111098 
 PCKRDY7PCKRDY6PCKRDY5PCKRDY4PCKRDY3PCKRDY2PCKRDY1PCKRDY0 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 OSCSELS   MCKRDY  MOSCXTS 
Access RRR 
Reset 010 

Bit 26 – MCKXRDY Main System Bus Clock x Ready Status

ValueDescription
0 At least one main system bus clock is not established.
1 All main system bus clocks are established.

Bit 25 – PLL_INT PLL Interrupt Status

ValueDescription
0 No PLL interrupt has occurred.
1 A PLL interrupt has occurred. PLL interrupt is defined by the configuration of PMC_IMR.

Bit 24 – GCLKRDY GCLK Ready

ValueDescription
0 A GCLK is not ready to use (clock switching in progress).
1 All GCLKs are switched to their selected source clock and ready to use.

Bit 23 – MCKMON Main System Bus Clock0 Clock Monitor Error

This status is cleared on read.

ValueDescription
0 Main system bus clock0 is correct or the CPU clock monitor is disabled.
1 Main system bus clock0 is incorrect or has been incorrect for an elapsed period of time since the monitoring has been enabled.

Bit 21 – XT32KERR Slow Crystal Oscillator Error

ValueDescription
0 The frequency of the 32.768 kHz crystal oscillator is correct (32.768 kHz ±1%) or the monitoring is disabled.
1 The frequency of the 32.768 kHz crystal oscillator is incorrect or has been incorrect for an elapsed period of time since the monitoring has been enabled.

Bit 20 – FOS Clock Failure Detector Fault Output Status

ValueDescription
0 The fault output of the clock failure detector is inactive.
1 The fault output of the clock failure detector is active. This status is cleared by writing a ‘1’ to FOCLR in PMC_FOCR.

Bit 19 – CFDS Clock Failure Detector Status

ValueDescription
0 A clock failure of the main crystal oscillator clock is not detected.
1 A clock failure of the main crystal oscillator clock is detected.

Bit 18 – CFDEV Clock Failure Detector Event

ValueDescription
0 No clock failure detection of the main crystal oscillator clock has occurred since the last read of PMC_SR.
1 At least one clock failure detection of the main crystal oscillator clock has occurred since the last read of PMC_SR.

Bit 17 – MOSCRCS Main RC Oscillator Status

ValueDescription
0 The main RC oscillator is not stabilized.
1 The main RC oscillator is stabilized.

Bit 16 – MOSCSELS Main Clock Source Oscillator Selection Status

ValueDescription
0 Selection is in progress.
1 Selection is done.

Bits 8, 9, 10, 11, 12, 13, 14, 15 – PCKRDYx Programmable Clock Ready Status

ValueDescription
0 Programmable clock x is not ready.
1 Programmable clock x is ready.

Bit 7 – OSCSELS Timing Domain Slow Clock Oscillator Selection

ValueDescription
0 The embedded slow RC oscillator is selected.
1 The 32.768 kHz crystal oscillator is selected.

Bit 3 – MCKRDY Main System Bus Clock 0 Status

ValueDescription
0 Main system bus clock 0 is not ready.
1 Main system bus clock 0 is ready.

Bit 0 – MOSCXTS Main Crystal Oscillator Status

ValueDescription
0 The main crystal oscillator is not stabilized.
1 The main crystal oscillator is stabilized.