1.5.4.5 Reference Clock Disruptions

Reference clocks are required to be applied and stable to the PLLs for proper transceiver operations for Lock to Data or Lock to Reference applications. TXPLL and RXCDR PLL require a guaranteed reference clock to ensure proper operation. Reference clock inputs does not include any “signal detection”. It is the responsibility of the user design to monitor and handle losses or switching of the system level reference clocks. Reference clock disruptions can cause the lock control circuitry to misbehave and possibly be stuck into whatever state it is in when the reference clock is lost.