1.5.4.2 Broadcasting REFCLK to the FPGA Fabric

In the PolarFire family devices, you can broadcast the external XCVR reference clock (REFCLK) signal into the FPGA fabric using a hardwired global routing resource. This is possible when the following conditions are met:
  1. The selected XCVR quad (Q#) is not configured to use global output clocks. This ensures that the global output is available for broadcasting the REFCLK. Use regional clock outputs for XCVR related clock outputs from the selected quad.
  2. The external REFCLK enters the device using a XCVR_#A_REFCLK_P/N input pin (not XCVR_#B_REFCLK nor XCVR#C_REFCLK pins)
    • Assigning the REFCLK input to the XCVR_#A_REFCLK_P/N input ensures that the selected XCVR_REF_CLK corresponds to a location associated with the TXPLL_SSC in the XCVR quad.
    • The XCVR_REF_CLK associated with a quad’s TXPLL_SSC has additional connectivity to the fabric global clocking resources through the east Interface Clock Block (ICB), as described in Reference Clock Input Pins and in the “Global Clock Network” section of the PolarFire Family Clocking Resources User Guide.
    • The XCVR_REF_CLK can simultaneously broadcast the REFCLK to the FPGA fabric and drive either the selected quad’s TXPLL_SSC or a Q#_TXPLL#, per allowable placements in the Libero SoC I/O Editor XCVR View.
  3. Instantiate and connect a CLKINT_PRESERVE macro to the XCVR_REF_CLK hardwired output port REF_CLK. This ensures that the hardwired connection is preserved during Synthesis optimizations.

The following table lists the conditions that are listed in the preceding list and the resulting Global Net Report.

Table 1-19. Selecting XCVR_#A_REFCLK_P/N Inputs on a XCVR QUAD# Using Package Pin Assignment Table
Package PinsMPF300T/MPF300TS-FCG1152 Pin Names
AF29XCVR_2B_REFCLK_P
AF30XCVR_2B_REFCLK_N
AE27XCVR_2A_REFCLK_P
AE28XCVR_2A_REFCLK_N
AC27XCVR_2C_REFCLK_P
AC28XCVR_2C_REFCLK_N

The following figures show the conditions that are listed in the preceding list and the resulting Global Net Report.

Figure 1-44. Using Libero SoC I/O Editor XCVR View to Place the REFCLK, TXPLL, and XCVR Q#
Figure 1-45. Schematic View Showing XCVR_REF_CLOCK Driving XCVR/TXPLL and Fabric Logic (through CLKINT_PRESERVE)
Table 1-20. Libero SoC Global Net Report Confirming the Hardwired Connection from XCVR REFCLK to Fabric CLKINT
FromFrom LocationToNet NameNet TypeFanout
OSC_0_0/OSC_0_0/I_OSC_160:CLK(512, 2)PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3/U0OSC_0_0_RCOSC_160MHZ_CLK_DIVHARDWIRED2
xcvr_ref_clock_0/xcvr_ref_clock_0/I_IO:REFCLK_0(2466, 371)CLKINT_PRESERVE_0/U0xcvr_ref_clock_0_REF_CLKHARDWIRED3
OSC_0_0/OSC_0_0/I_OSC_160:CLK(512, 2)OSC_0_0/OSC_0_0/I_OSC_160_INT/U0OSC_0_0_RCOSC_160MHZ_CLK_DIVHARDWIRED2