1.5.4.1 Transceiver Reference Clock Interface

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The reference clock interface block to the transceiver provides multiple options for supplying the reference clock input to the transceiver transmit and receive PLLs (Figure 1). Various sources can provide the reference clock interface through REFCLK0 and REFCLK1 ports.

Differential dedicated input pad: allows a direct clock input of a low-jitter reference clock through a LVDS/HCSL input pins REFCLK_P/N.
Single-ended dedicated input pad(s): allows the selection from two different single-ended clock inputs, enabling the transmit PLL to select from two different clock sources. Separate single-ended clock inputs allow unrelated transmit and receive clock sources to be sourced to the transceiver.

Important: Two separate single-ended inputs allow one for the transmit reference clock and a second for the receive reference clock.

Cascade of a reference clock: the clock received on the external pins of a quad can be driven to the quad below. The reference clock interface provides cascading of an input reference clock path from the REFCLK pins of one transceiver quad to the TxPLLs and receiver CDRs of other transceivers. In designs that have lanes spanning different transceiver quads, the cascading clocks eliminate the need to connect the on-board reference clock sources to the REFCLK pin of each transceiver quad. The reference clock interface also drives a clock signal on the REFCLK pins to the clock logic in the FPGA fabric.
Recovered clock: allows for the reference clock to be sourced by the recovered clock from local quad (through JA_REF_CLK). Within a Quad, the recovered clock used as JA_REF_CLK has dedicated connections between the lanes without any additional jitter. For inter-quad or using the recovered clock from one Quad to the JA_REF_CLK of another Quad, this has added jitter from using routing of the FPGA fabric. Since this clock is from the noisy digital VDD/VSS domain on the device, the reference clock jitter is higher than the dedicated inputs. Generally used with the jitter attenuation feature.

Important: The reference clock driving the transmit PLL REF_CLK also serves each lane for the receive CDR. Since each receive lane has an independent PLL, it is possible to use an independent reference clock per receive lane. PLL for the CDR is per transceiver PMA lane.

The PF_XCVR_REF_CLK does allow the FAB_REF_CLK output pin to drive a fabric global resource. This connection is limited to one per quad and if used, it prevents using the global of a XCVR lane in the same quad. However, you can connect XCVR_ FAB_REF_CLK output pin to PLL and one lane to global at the same time. For information about implementation of this connection, see Transceiver Reference Clock Configurator.

Figure 1-43. Reference Clock (REFCLK) Interface to Transmit PLL

The following table lists the transmit PLL pins.

Table 1-18. Transmit PLL Pin List¹
Name	Direction	Description
REF_CLK	Input	Transmit PLL input clock from reference clock interface (Figure 1).
PLL_LOCK	Output	PLL_LOCK is the PLL lock indicator signal that can be used to drive logic in the fabric. It is a fabric routed signal.  (High = LOCK).
CLKS_TO_XCVR	Output	CLKS_TO_XCVR is a bus interface port (BIF) with three outputs that are required to be interconnected between the TXPLL and the XCVR components. The BIF includes BIT_CLK, LOCK, and REF_CLK_TO_LANE outputs.
BIT_CLK²	Output	High-speed clock to lane.
LOCK²	Output	Connected to the TX_PLL_LOCK_0/1 input port, which is a part of the CLKS_FROM_TXPLL_0/1 BIF on the XCVR block. It is a hardwired connection.
REF_CLK_TO_LANE²	Output	Connected to the TX_PLL_REF_CLK_0/1 input port, which is a part of the CLKS_FROM_TXPLL_0/1 BIF on the XCVR block. It is a hardwired connection. TXPLL reference clock that is passed to the XCVR lane clock (used for simulation only)
CLK_125	Output	Exposed directly on the TXPLL block. Its frequency is fixed at  125 MHz. It is exposed only when the TXPLL BIT_CLK is  2500 Mbps, and must be used for a PCIe use case.
⁽¹⁾ Pin list for both Q#_TxPLL[1:0] and Q#_TxPLL_SSC PLLs. ⁽²⁾ Port is a part of the bus interface port (BIF) CLKS_TO_XCVR.

There are some use-cases which can allow a XCVR quad's global output to be used to broadcast the SerDes REFCLK, if that XCVR is configured to use regional clocks for the TX/RX clocks allowing these specific use-cases to broadcast the SerDes REFCLK into the FPGA fabric with a more predictable amount of clock jitter.