1.5.4.4 Dedicated Reference Clock Input Pins

For every transmit PLL within the transceiver PMA, there is a reference input pin pair for an external input of reference clocks to the device, as shown in the following figure. The reference clock inputs provide flexibility to interface with both single-ended and differential clocks and can drive up to two independent clocks per transceiver quad. The reference clock inputs has a single power supply (VDD_XCVR_CLK) that is shared across all reference clock buffers. These reference clocks can also be sourced for the global and regional clock networks in the FPGA fabric of the devices.

The following figure provides a detailed view of the dedicated reference clock.