The high-level steps for SmartHLS™ to generate a RISC-V reference SoC is shown below. It receives a C/C++ program as input, where user has specified one or more functions to accelerate in hardware with the pragma, #pragma HLS function top. Clang, the frontend compiler, transforms the input program to call the generated software drivers functions. The software driver functions handle data transfers from DDR to hardware accelerators, invoke the hardware accelerators, and retrieve any computed results. The transformed software and generated software driver functions form the software partition, which is compiled with the RISC-V compiler toolchain into a software binary to execute on the RISC-V MSS. The hardware partition goes through a series of compiler optimizations that optimize the partition for hardware acceleration. The hardware generation step generates hardware accelerators in Verilog. It also generates Tcl scripts that contains commands for SmartDesign, which is run to integrate the hardware accelerators and any additional IPs to generate a complete SoC comprising the RISC-V MSS, interconnect, and hardware accelerators.
