3.6.2.4.4 ENABLE_AUTOMATIC_MULTIPLY_MODE_SETTING
(Ask a Question)Enable determining multiply mode automatically according to the target clock period and timing model of the board. Fully pipelined mode (i.e., using both input and output registers of each Math block) will be used when the target clock period is less than the delay of a Math block, otherwise half pipelined mode (i.e., using only the input register of each Math block) will be used.
Fully pipelined mode can result in higher circuit Fmax at the expense of higher circuit
latency. This functionality is disabled when set_resource_constraint multiply
X or set_operation_latency multiply X is defined. The
threshold for switching are listed in the table below.
| Device | Fully Pipelined Mode when Target Period is less than (ns) |
|---|---|
| PolarFire®, PolarFireSoC | 3.704 |
| IGLOO2, SmartFusion® 2 | 4.169 |
Below is a table of latency for multiplications of unsigned integers for selected bit widths for reference:
| (Bit Width) x (Bit Width) = (Bit Width) | Half Pipelined Mode Latency | Full Pipelined Mode Latency |
|---|---|---|
| 8 x 8 = 8 | 1 | 2 |
| 8 x 8 = 16 | 1 | 2 |
| 16 x 16 = 16 | 1 | 2 |
| 16 x 16 = 32 | 1 | 2 |
| 32 x 32 = 32 | 2 | 4 |
| 32 x 32 = 64 | 3 | 5 |
| 64 x 64 = 64 | 6 | 11 |
| 64 x 64 = 128 | 9 | 17 |
- Category
- HLS Constraints
- Value Type
- Boolean
- Valid Values
- 0, 1
- Default Value
- 1
- Location Where Default is Specified
examples/legup.tcl- Dependencies
- None
- Applicable Flows
- All devices and flows
- Test Status
- Actively in-use
- Examples
set_parameter ENABLE_AUTOMATIC_MULTIPLY_MODE_SETTING 1