3.6.2.4.20 SYNTHESIS_CLOCK_PERIOD
(Ask a Question)This constraint allows the user to override the SDC clock period constraint for synthesis, P&R, and timing analysis.
By default, when this constraint is not specified, the same CLOCK_PERIOD constraint for HLS is used for the SDC clock period constraint. However, it may be useful to give a tighter SDC clock period constraint to close timing.
The clock period is specified in nanoseconds.
- Category
- HLS Constraints
- Value Type
- Integer; represents a value in nanoseconds
- Valid Values
- Integer
- Default Value
- N/A
- Dependencies
- None
- Applicable Flows
- All devices and flows
- Test Status
- Actively in-use
- Examples
set_parameter SYNTHESIS_CLOCK_PERIOD 10