43.4 Power Supply Electrical Specifications

Table 43-5. Power Supply Electrical Specifications
AC Characteristics			Standard Operating Conditions: V_DDIO = V_DDANA 1.9-3.6V (unless otherwise stated) Operating Temperature: -40°C ≤ T_A ≤ +85°C for Industrial Temp -40°C ≤ T_A ≤ +125°C for Extended Temp
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
REG_1	VDDCORE_C_IN	VDDCORE (CLDO_OUT) input bypass parallel capacitor pair⁽⁵⁾	—	1	—	µF	Bulk ceramic or solid tantalum with ESR <0.5Ω. Min and max represent absolute values including cap tolerances
REG_1	VDDCORE_C_IN	VDDCORE (CLDO_OUT) input bypass parallel capacitor pair⁽⁵⁾	—	100	—	nF	Ceramic XR7/X5R with ESR <0.5Ω depending on temperature
REG_5	VDD33	VDD33 input bypass parallel capacitor pair⁽⁵⁾	—	10	—	μF	Bulk ceramic or solid tantalum with ESR <0.5Ω⁽⁵⁾
REG_5	VDD33	VDD33 input bypass parallel capacitor pair⁽⁵⁾	—	100	—	nF	Ceramic XR7/X5R with ESR <0.5Ω depending on temperature on all VDDIO pins⁽⁵⁾
REG_6	PMU_VDDIO	Input bypass parallel capacitor pair for the PMU power section⁽⁵⁾	—	4.7	—	μF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω⁽⁵⁾
REG_7	PMU_VDDP	Input bypass parallel capacitor pair for the PMU power section⁽⁵⁾	—	1	—	μF	Bulk ceramic or solid tantalum with ESR <0.5Ω⁽⁵⁾
REG_9	VDDFLASH_C_IN	VDD_FLASH bypass parallel capacitor pair⁽⁵⁾	—	10	—	μF	Bulk ceramic or solid tantalum with ESR <0.5Ω⁽⁵⁾
REG_9	VDDFLASH_C_IN	VDD_FLASH bypass parallel capacitor pair⁽⁵⁾	—	100	—	nF	Ceramic XR7/X5R with ESR <0.5Ω depending on temperature on all VDDFLASH pins⁽⁵⁾
REG_17	VDDANA_C_IN	VDDANA input bypass parallel capacitor pair⁽⁵⁾	—	10	—	μF	Bulk ceramic or solid tantalum with ESR <0.5Ω⁽⁵⁾
REG_17	VDDANA_C_IN	VDDANA input bypass parallel capacitor pair⁽⁵⁾	—	0.1	—	nF	Ceramic XR7/X5R with ESR <0.5Ω
REG_18	VDDANA_LEXT	VDDANA series ferrite bead DCR (DC resistance)	—	—	0.1	Ω	≥600Ω at 100 MHz
REG_19	VDDANA_LEXT	Ferrite bead current Rating⁽¹⁾	100	—	—	mA	—
REG_20	BUCK_PLL_CIN	VDD bypass capacitor on the BUCK_PLL input	—	1	—	μF	Ceramic XR7/X5R with ESR <0.5Ω
REG_21	BUCK_BB_CIN	VDD bypass capacitor on the BUCK_BB input	—	1	—	μF	Ceramic XR7 with ESR <0.5Ω
REG_22	BUCK_MPA_CIN	VDD bypass capacitor on the BUCK_LPA input	—	1	—	μF	Ceramic XR7 with ESR <0.5Ω
REG_23	BUCK_LPA_CIN	VDD bypass capacitor on the BUCK_MPA input	—	1	—	μF	Ceramic XR7 with ESR <0.5Ω
REG_24	BUCK_CLDO_CIN	VDD bypass capacitor on the BUCK_CLDO input	—	1	—	μF	Ceramic XR7 with ESR <0.5Ω
REG_25	R_EXT	Bias for reference current generation	—	30	—	kΩ	—
REG_27	VSW_L_EXT^(2,3)	Buck Switch mode regulator inductor inductance	—	4.7	—	μH	Shielded inductor only
REG_29		Inductor DCR (DC resistance)	—	—	0.22	Ω	—
REG_31		Inductor I_SAT rating^(2,6)	250	—	—	mA	—
REG_32	VSW_CAPEXT	Buck Switch mode regulator bulk capacitor capacitance	10	—	—	μF	—
REG_32A	VSW_CAPEXT	Buck Switch mode regulator filtering capacitor capacitance	100	—	—	nF	—
REG_36	VDDCORE	VDDCORE voltage range	1.14	1.2	1.26	V	MCU Active, cache and prefetch disabled while executing from Flash
REG_37	VDD33⁽⁴⁾	VDD33 input voltage range	1.9	3.3	3.6	V	—
REG_39	VDDANA⁽⁴⁾	VDDANA input voltage range	1.9	3.3	3.6	V	—
REG_40	VDD_PMU	PMU output voltage	1.30	1.35	1.40	V	PMU output voltage
REG_43	SVDDIO_R	VDDIO rise ramp rate to ensure internal Power-on Reset signal	0.03	—	0.11	V/ms	Failure to meet this specification may lead to start-up or unexpected behaviors
REG_44	SVDDIO_F	VDDIO falling ramp rate to ensure internal Power-on Reset signal	—	—	1.39	V/ms	Failure to meet this specification may cause the device to not detect reset
REG_45	VP0R+	Power-on Reset	—	1.59	—	V	VDDIO power up/Down (See Param REG43, VDDIO Ramp Rate)
REG_45_A	VP0R-	Power-on Reset	—	1.56	—	V	VDDIO Power up/Down (See Param REG43, VDDIO Ramp Rate)
REG_47	VBOR33⁽⁴⁾	VDDIO BOD	—	1.8	—	V	—
REG_48	VBOR12	BOR of the 1.2V regulator	—	1.1	—	V	—
REG_48A	VZPBOR33	Zero power BOR	2.1	—	—	V	Function available from 2.1V to 3.6V. Applicable for deep sleep wake-up condition.
REG_49	VBOR33L2H	BOR 3.3V low to high switch point	—	1.84	—	V	—
REG_50	VBOR1P2L2H	BOR 1.2V low to high switch point	—	1.1	—	V	—
REG_51	VBOD12	VBOD12 Hysteresis	—	10.5	—	mV	—
REG_52	VBOD33	VBOD33 Hysteresis	—	51.6	—	mV	—
REG_53	TRST⁽⁶⁾	External RESET valid active pulse width	—	11	—	µs	Minimum Reset active time to guarantee MCU Reset for the module. Reset filter circuit inside Module
REG_53	TRST⁽⁶⁾	External RESET valid active pulse width	—	2.7	—	µs	Minimum Reset active time to guarantee MCU Reset for SoC with no Reset filter circuit
Note: Ferrite Bead ISAT(min) ≥ (IDDANA(max) * 1.15). Buck Inductor ISAT(min) ≥ ((ICAPACITOR + IVDDCORE_MAX) * 1.2) when the BUCK mode is enabled (shielded inductor only). User must select either LDO or BUCK Mode. The modes are exclusive to each other. VDD33 and VDDANA must be at the same voltage level. All bypass caps must be located immediately adjacent to pin(s) and on the same side of the PCB as the MCU. Each primary power supply group VDDIO, VDDANA, VDDCORE must have one bulk capacitor and all power pins with a 100 nF bypass cap. The RESET pulse width is the minimum pulse width required on the I/O pin after any filtering on the MCLR pin. Keep the DCR as low as possible to improve efficiency. These parameters are characterized but not tested in manufacturing.