3.6.14 `CNFG_GetSPIConfiguration` Command and its Response

The CNFG_GetSPIConfiguration command (0xAF) reads the SPI Configuration from SRAM or NVM:

bSource → 0x00 = SRAM; 0x01 = NVM

This command is sent through Endpoint 0x05 (OUT). The response is read through Endpoint 0x85 (IN).

Table 3-33. `CNFG_GetSPIConfiguration` - Command
Byte Index	Command		Description
0	`0xAF`	Command code	Returns the SPI configuration from SRAM or NVM
1	`0x00` `0x01`	bSource: SRAM NVM

Table 3-34. `CNFG_GetSPIConfiguration` - Response
Byte Index	Response		Description
0	`0xAF`	Echo command code	Returns the SPI configuration from SRAM or NVM
1	`0x21`	Accepted	Command is accepted
2	`0x30` `0x20` `0x32` `0x22` `0x34` `0x24` `0x26`	Speed: 12 MHz 6 MHz 3 MHz 1.5 MHz 750 kHz 375 kHz 187.5 kHz	SPI clock frequency
3	`0x44` `0x45` `0x46` `0x47`	Mode: 0 1 2 3	SPI mode
4	`0x00` `0x01` `0x40` `0x41` `0x80` `0x81` `0xC0` `0xC1`	CS-ActStat: CS0-ActiveLow CS0-ActiveHigh CS1-ActiveLow CS1-ActiveHigh CS2-ActiveLow CS2-ActiveHigh CS3-ActiveLow CS3-ActiveHigh	Chip-select and its assertion state
5	`0x0000` `0x000A` `0x0014` `0x001E` `...` `0x03E8` `…` `0x1388`	0 μs 10 μs 20 μs 30 μs ... 1000 μs ... 5000 μs	Delay between chip-select assertion and the first data byte Delay between each data byte Delay between the last data byte and chip select de-assertion.

DS40002695A

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